Robust and Power-Aware Design of CNFET-Based XOR Circuit at 16-nm Technology Node

Motivations of CMOS technology scaling are higher speed of operation, benefit of integration density and lower power dissipation. CMOS technology has crossed many hurdles over the past four decades. The aggressive technology scaling is causing device parameter variations, which is more severe than earlier. This paper carries out variability analysis of various popular exclusive-OR circuits at the transistor level in terms average power and powerdelay product (PDP) at 16-nm technology node. A simulation framework, consisted of the gate under test loaded with two nominal copies of the corresponding XOR gate at both the ends – input and output, is used for the analysis. The aim of this work is to determine the circuit with least variability of PDP. Finally, it realizes the best XOR circuit using an emerging device namely carbon nanotube field effect transistor (CNFET). At nominal supply voltage of VDD = 0.7 V, the proposed CNFET based realization of XOR circuit offers 1.63 × improvement in PDP variability and 6.15 × improvement in PDP compared to its CMOS counterpart. Keywords— carbon nanotube field effect transistor (CNFET), low-power, power delay product (PDP), propagation delay, robust, variability.